DFT Engineer/ Senior DFT Engineer (Semiconductor Design) - Engineering - iTest Bangladesh Limited

Job Description

Title: DFT Engineer/ Senior DFT Engineer (Semiconductor Design) - Engineering - iTest Bangladesh Limited

Company Name: iTest Bangladesh Limited

Vacancy: 2

Age: Na

Job Location: Dhaka (Mohakhali)

Salary: Negotiable

Experience:

• 3 to 5 years

• Master of Science (MSc) in Electrical & Electronic Engineering, Computer Science & Engineering
• Bachelor of Science (BSc) in Electrical & Electronic Engineering, Computer Science & Engineering

• 3 to 5 years

• 3–5 years of experience in DFT / VLSI Design

• Strong hands-on experience with Tessent (Mentor/Siemens) tool suite

• Expertise in Memory BIST (MBIST) architecture and implementation

• Experience in pattern generation, validation, and tester bring-up

• Proficiency in Verilog/SystemVerilog for DFT/test logic

• Good understanding of scan, ATPG, and DFT methodologies

• Experience working with ATE and silicon debug (SI analysis)

• Experience with SoC-level DFT integration

• Familiarity with timing closure and physical-aware DFT

• Strong debugging and problem-solving skills

• Familiarity with synthesis and physical design flows (PnR)

• Knowledge of scripting (Tcl/Python)

About the company: iTest Bangladesh Ltd. is a local business enterprise of iTest Inc., Headquarters in USA and is pioneers in the art and science of IC Testing - a reliable partners from development through production and a team with a track record of redefining a Test-Lab. Its mission is critical solution when second-best is not an option.

The vision of iTest Bangladesh Ltd. are driven to earn customers' trust and fascination with commitment to quality, dependability and cost competitiveness.

Website: https://itest.mj-group.com/

Job Responsibilities:

• Work extensively with Tessent tools for Memory BIST (MBIST) enablement, configuration, and validation;

• Generate, validate, and debug test patterns, ensuring successful porting to ATE (tester) platforms;

• Analyze silicon (SI) data and debug test failures to improve coverage and yield;

• Develop and integrate DFT structures using Verilog (scan, MBIST, etc.);

• Support verification of DFT logic at RTL and gate level;

• Collaborate with synthesis and physical design (PnR) teams to ensure smooth DFT implementation and closure;

• Participate in DFT planning, insertion, and sign-off activities;

• Debug issues across the flow from RTL to silicon.

• Mobile bill,Weekly 2 holidays,Medical allowance,T/A
• Lunch Facilities: Full Subsidize
• Salary Review: Yearly
• Festival Bonus: 2

• Transportation Facility/ Pick & Drop Earned Leave Encashment Lunch Facilities: Full Free Earned Leave Encashment