Title: Junior Engineer/Engineer - RTL Synthesis & STA
Company Name: An Emerging Semiconductor Company
Vacancy: --
Age: Na
Job Location: Dhaka
Salary: Negotiable
Experience:
● Perform RTL synthesis using Xilinx Vivado and generate gate-level netlists.
● Conduct static timing analysis (STA) to ensure designs meet performance requirements.
● Optimize designs for timing, area, and power.
● Apply timing constraints (SDC/XDC) and debug timing violations (setup, hold, recovery, removal).
● Collaborate with design teams to resolve synthesis and timing closure issues.
● Support FPGA implementation flows, including bitstream generation and validation.
● 1–3 years of experience in RTL synthesis and STA.
● Strong understanding of digital design concepts (clocking, resets, timing paths, pipelining, metastability).
● Hands-on experience with Xilinx Vivado (synthesis, implementation, timing analysis).
● Familiarity with STA concepts (setup/hold time, slack, clock skew, false/multicycle paths).
● Basic knowledge of constraints (SDC/XDC).
● Good understanding of Verilog/VHDL RTL coding for synthesis.
● Strong problem-solving and debugging skills.
● Exposure to ASIC flows with tools like Synopsys Design Compiler or Cadence Genus.
● Knowledge of low-power design techniques and optimization strategies.
● Familiarity with FPGA hardware bring-up and lab testing.
● Scripting skills (TCL, Python, Shell) for flow automation.