Title: Junior Engineer/Engineer - RTL Design & Synthesis
Company Name: An Emerging Semiconductor Company
Vacancy: --
Age: Na
Job Location: Dhaka
Salary: Negotiable
Experience:
● Design, develop, and verify Register Transfer Level (RTL) modules for digital hardware.
● Perform logic synthesis, timing checks, and optimizations using Xilinx Vivado.
● Simulate and debug RTL functionality using Icarus HDL (iverilog) or equivalent tools.
● Collaborate with verification engineers to resolve functional and timing issues.
● Document design specifications and support block/system-level integration.
● 1–3 years of hands-on experience in RTL design using Verilog/VHDL/SystemVerilog.
● Solid understanding of digital design fundamentals (combinational/sequential logic, FSMs, pipelining, clocking, resets).
● Experience with Xilinx Vivado (synthesis, implementation, timing analysis).
● Experience with Icarus HDL (iverilog) or other RTL simulation tools.
● Familiarity with version control systems (e.g., Git) and basic Linux shell usage.
● Strong analytical, debugging, and problem-solving skills.
● Exposure to FPGA-based prototyping and bitstream generation.
● Knowledge of scripting languages (TCL, Python, or Shell) for design automation.
● Understanding of low-power design techniques and constraints.
● Experience with industry-standard verification methodologies (UVM, functional coverage, assertions)