Title: Junior Engineer/Engineer - Design Verification
Company Name: An Emerging Semiconductor Company
Vacancy: --
Age: Na
Job Location: Dhaka
Salary: Negotiable
Experience:
● Develop and execute testbenches for RTL design verification using Verilog/SystemVerilog.
● Perform simulation and debugging of RTL code using Icarus HDL (iverilog) or equivalent tools.
● Run functional verification, generate test vectors, and validate designs against specifications.
● Use Xilinx Vivado for simulation, analysis, and FPGA-based validation.
● Work closely with RTL designers to identify, reproduce, and resolve functional and timing issues.
● Document verification plans, test cases, and results.
● 1–3 years of experience in RTL verification with Verilog/VHDL/SystemVerilog.
● Strong understanding of digital design fundamentals (logic gates, FSMs, clocking, resets, timing).
● Hands-on experience with simulation tools such as Icarus HDL (iverilog), ModelSim, or Questa.
● Familiarity with Xilinx Vivado for simulation and FPGA-based testing.
● Knowledge of basic testbench structures (stimulus generation, checkers, scoreboards).
● Strong debugging and problem-solving skills.
● Exposure to constrained random verification and coverage-driven methodologies.
● Familiarity with UVM/SystemVerilog verification methodologies.
● Experience with scripting languages (Python, TCL, or Shell) for automation.
● Exposure to FPGA prototyping and hardware bring-up.